Syllabus - Digital Logic Design

 

 

Time / Location:

        四電子一A (1403) : Wed. 17:10 – 18:00 (ES101) / Tue. 8:10 – 10:00 (ES101)

四電子一B (1404) : Wed. 13:10 – 14:00 (ES101) / Wed. 8:10 – 10:00 (ES101)

 

Instructor: 蘇慶龍  Email: kevinsu@yuntech.edu.tw

 

Office: ES-903 Phone: 05-5312601 ext:4328

 

Office Hours: Tue. 13:10~16:00

 

TA 1: E-mail: g9313737@yuntech.edu.tw Phone: 05-5312601 ext:4380

TA 2: E-mail: g9313714@yuntech.edu.tw Phone: 05-5312601 ext:4380

 

Prerequisites: Nil

 

Text Book:

        Digital Design, 3rd Edition, M. Morris Mano, 2002, 1991, 1984 Prentice-Hall, Inc.

 

Reference Book:

        Fundamentals of Logic Design, 5th Edition, Charles H. Roth, Jr., 2004 Brooks/Cole

 

Course Contents:

1. Binary Systems

2. Boolean Algebra and Logic Gates

3. Gate-level Minimization

4. Combinational Logic

5. Synchronous Sequential Logic

6. Registers and Counters

7. Memory and Programmable Logic

8. Register Transfer Level

9. Asynchronous Sequential Logic

10. Digital Integrated Circuit

 

Grading:

Chapter Exam. 30%

1st. Midterm Exam: 20%

2nd. Midterm Exam: 20%

Final Exam: 30%

 

On-Line Resources:

1. http://www.cic.edu.tw

2. EECS, SoC Lab.