Syllabus – Hardware Description Language Design and Simulation

 

 

Time / Location:

        四電子二 (1456) : Mon. 09:00 – 12:00 (ES001)

 

Instructor:

蘇慶龍  Email: kevinsu@yuntech.edu.tw

 

Office Hours:

        Tue. 10:00 – 12:00 (ES903)

 

Lab Time:

        ? (ES303)

 

Office: ES-903 Phone: 05-5312601 ext: 4328

 

Prerequisites: Nil

 

Text Book:

Verilog HDL: A Guide to Digital Design and Synthesis, 2nd Edition, Samir Palnitkar, 2003, Prentice-Hall, Inc. (全華圖書)

 

Reference Book:

The Verilog HDL, 5th Edition, Donald E. Thomas, Philip R. Moorby, Donald B. Thomas, 2002, Kluwer Academic Publication.

 

Course Contents:

 

I. BASIC VERILOG TOPICS.
1. Overview of Digital Design with Verilog HDL.
2. Hierarchical Modeling Concepts.
3. Basic Concepts.
4. Modules and Ports.
5. Gate Level Modeling.
6. Data Flow Modeling.
7. Behavioral Modeling.
8. Tasks and Functions.
9. Useful Modeling Techniques.


II. ADVANCED VERILOG TOPICS.
10. Timing and Delays.
11. Switch Level Modeling.
12. User Defined Primitives
13. Programming Language Interface.
14. Logic Synthesis with Verilog HDL.

 

Grading:

Ordinary Test 50%

Midterm Exam: 20%

Final Exam: 30%

 

On-Line Resources:

1. http://www.cic.edu.tw

2. http://soc.eecs.yuntech.edu.tw