期刊論文:

【1】Ching-Lung Su, “The bottleneck and performance analysis for the MPEG embedded system SoC hardware and software design,” Journal of Institute of Information & Computing Machinery, Invited paper, June 2007

【2】
Chih-Da Chien, Keng-Po Lu, Yu-Min Chen, Jiun-In Guo, Yuan-Sun Chu, and Ching-Lung Su, “An Efficient Variable Length Decoder IP Core Design for MPEG-1/2/4 Video Coding Applications, “ IEEE Trans. Circuits & Systems for Video Technology, vol. 16, no. 9, pp. 1172-1178, Sept. 2006

【3】Ching-Long Su
and Chein-Wei Jen, "Motion estimation using MSD-First processing," IEE Proceedings G- Circuits, Devices and Systems, vol. 150, no. 2, pp. 124-133, Apr. 2003

【4】Ching-Long Su
and Chein-Wei Jen, "MSD-first On-line Arithmetic Progressive Processing Implementation for Motion Estimation," IEICE Trans. on Information & Systems, vol. E86-D, no. 11, pp. 2433-2442, Nov. 2003


會議論文:

【1】Hsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li1, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shan Wang, and Jiun-In Guo, "A 7-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip", IEEE International Solid-State Circuits Conference (ISSCC), pp. 280-281, 603, Feb. 2007.

【2】Ching-Lung Su
, Wei-Sen Yang, Ya-Li Chen, Ching-Wen Chen, Yao Li, Ching-Wen Chen and Jiun-In Guo, “Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2006, Invited Paper, pp. 578-581, Dec. 2006.

【3】Ching-Lung Su
, Wei-Sen Yang, Ya-Li Chen, Yao-Chang Yang, Ching-Wen Chen, and Jiun-In Guo, “A Low Complexity High Quality Integer Motion Estimation Architecture Design for H.264/AVC,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2006, pp. 398-401, Dec. 2006.

【4】
Dear Yao-Chang Yang, Chien-Chang Lin, Hsui-Cheng Chang, Ching-Lung Su, and Jiun-In Guo,“A High Throughput VLSI Architecture Design for H.264 Context-based Adaptive Binary Arithmetic Decoding with Lookahead Parsing,” IEEE International Conference on Multimedia & Expo (ICME),  pp. 357-360, July 2006.

【5】
Yi-Ting Hong, Ze-Ming Chen, Wei-Sen Yang, Guo-Zhen Wu, Jun-Yu Yang, Guan-Wei Fan, and Ching-Lung Su, “A Linux Embedded System Implementation to an ARM-based SoC Prototype and Its HW/SW Performance Optimization for the MPEG-4 Simple Profile Level 2 Decoder,” 2005 Workshop on Consumer Electronics and Signal Processing, Yinlin, Taiwan, Nov. 2005

【6】
Chung-Lin Wu, Zhen-Yong Gao, and Ching-Lung Su, “A High-speed 2-D DCT/IDCT Architecture with Low Transpose Memory Requirements,” The 15th VLSI Design / CAD Symposium, Taiwan, Aug. 2004

【7】Ching-Long Su
and Chein-Wei Jen, “Motion Estimation with MSD-First Processing,” The 12th VLSI Design / CAD Symposium, Taiwan, Aug. 2001

【8】
 Ching-Long Su and Chein-Wei Jen, “Motion Estimation Using On-line arithmetic,” 2000 IEEE International Symposium on Circuits and Systems (ISCAS), Geneva, Switzerland, vol. I, pp. 683-686, May 2000

【9】Ching-Long Su
, Yin-Tsung Hwang and Chein-Wei Jen, “A Novel Recursive Digital Filter Based on Signed Digit Distributed Arithmetic,” 1997 IEEE International Symposium on Circuits and Systems (ISCAS), Hong Kong, China, vol. III, pp. 2104-2107, June 1997

【10】
Yin-Tsung Hwang and Ching-Long Su, “Parallel and Pipelined Architecture Designs for Distributed Arithmetic-Based Recursive Digital Filters,” 1996 IEEE Workshop on VLSI Signal Processing, San Francisco CA USA, Oct. 1996

【11】Ching-Long Su
and Yin-Tsung Hwang, “Distributed Arithmetic-Based Architectures for High Speed IIR Filter Design,” 1996 IEEE International Conference on Parallel and Distributed Systems (ICPADS), Tokyo Japan, pp. 156-161, June 1996

【12】
Yin-Tsung Hwang and Ching-Long Su, “A New Design Approach and VLSI Implementations of Recursive Digital Filters,” 1996 IEEE International Symposium on Circuits and Systems (ISCAS), Atlanta GA USA, vol. IV, pp. 304-307, May 1996

【13】Ching-Long Su
and Yin-Tsung Hwang, “Distributed Arithmetic Based Recursive Digital Filter Design for High Throughput Applications,” 1996 IEEE SOUTHEASTCON (SECON), Tampa FL USA, pp. 447-450, Apr. 1996

【14】 Ching-Long Su
and Yin-Tsung Hwang, “The Design & VLSI Implementation of A DA Look-Ahead Structure ARMA Filter,” The 7th VLSI Design / CAD Symposium, Taiwan, Aug. 1996

【15】
Yin-Tsung Hwang and Ching-Long Su, “Parallel and Pipelined VLSI Architecture Designs for Distributed Arithmetic-based Recursive Digital Filters,” International Computer Symposium, Taiwan, 1996

【16】Ching-Long Su
, Yin-Tsung Hwang, Ming-Kuen Chen and Chien-Ming Sun, “The Design & VLSI Implementation of A High Speed Low Chip Area ARMA Filter,” The 6th VLSI Design / CAD Symposium, Taiwan, 1995


專利:

【1】 Ching-Long Su, Jiun-In Guo, and Chin-Wen Chen, “適用於MPEG多媒體視訊編碼之低成本高畫質二階快速搜尋整數位移預測演算法 (A low cost high quality two-stage fast search integer motion estimation algorithm for MPEG video coding)”, USA/Taiwan Patent pending.

【2】 Ching-Long Su
, Jiun-In Guo, and Yaw Li , “高品質低複雜度H.264小數點精確度之移動估測演算法 (A low cost high quality fractional motion estimation algorithm for H.264),” USA/Taiwan Patent pending.

【3】 Ching-Long Su
, and Jiun-In Guo, “H.264高準度管線式編碼率控制演算法 (A high precision pipelined rate control algorithm for H.264),” USA/Taiwan Patent pending.

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